1. Field of the Invention
The present technology relates to the synthesis of an integrated circuit with sequential cells, with the goal of improved power/timing performance.
2. Description of Related Art
An integrated circuit design flow typically proceeds through the following stages: product idea, EDA software, tapeout, fabrication equipment, packing/assembly, and chips. The EDA software stage includes the steps shown in the following table:
EDA stepWhat HappensSystem DesignDescribe the functionality to implementWhat-if planningHardware/software architecture partitioningLogic Design andWrite VHDL/Verilog for modules in systemFunctionalCheck design for functional accuracy, does the design produceVerificationcorrect outputs?Synthesis andTranslate VHDL/Verilog to netlistDesign for TestOptimize netlist for target technologyDesign and implement tests to permit checking of the finishedchipDesign PlanningConstruct overall floor plan for the chipAnalyze same, timing checks for top-level routingNetlist VerificationCheck netlist for compliance with timing constraints and theVHDL/VerilogPhysicalPlacement (positioning circuit elements) and routing (connectingImplement.circuit elements)Analysis andVerify circuit function at transistor level, allows for what-ifExtractionrefinementPhysicalVarious checking functions: manufact., electrical, lithographic,Verfication (DRC,circuit correctnessLRC, LVS)ResolutionGeometric manipulations to improve manufacturabilityEnhanc. (OPC,PSM, Assists)Mask Data“Tape-out” of data for production of masks for lithographic use producePreparationfinished chips
In a typical circuit design process, a human designer runs an EDA (electronic design automation) tool which places a circuit design according to a computer implemented algorithm, including placement of the sequential cells of the circuit design. After the computer implemented placement, the human designer then manually checks and identifies the banks of sequential cells which cause poor results, such as bad timing or bad routability. This human process of trial and error is slow and expensive. Moreover, as the total number of cells in a circuit design approaches a significant fraction of a million cells, and even goes well into and beyond multiple millions, such a labor intensive process becomes even more error prone. Automated solutions also fall short, because automated solutions for placement and routing optimize parameters such as routability or timing, without accounting for further considerations such as low power. Modification of the automated solution, to add such considerations, has caused suboptimal results in the primary requirements such as routability or timing. Accordingly, the typical designer will rely on automated solutions to generate a design optimizing parameters such as routability or timing, and then manually modify the results, despite the labor intensive and error prone nature of such a process.
Various specific approaches which fail to meet expectations are further discussed below.
Manual selection and packing of groups of sequential cells have the drawbacks previously discussed. The major drawbacks are that the manual sequential cell banking process is tedious, time consuming and improbable to minimize the impact of sequential cell banking to timing and routability.
Another approach iterates between placement and clock-tree synthesis. Sequential cells driven by a clock-tree cell (buffer or ICG) are placed into a Manhattan circle with the center being the clock-tree cell. Manhattan circling may not save as much power as sequential cell banking because the net capacitance of a Manhattan circle usually exceeds the net capacitance of a sequential cell bank for driving the same number of sequential cells.
In another approach, a minimal number of links are added to a clock tree to reduce the clock tree's susceptibility to variation without paying the full power penalty of using clock meshes. However, analyzing the non-tree clock topologies using fast SPICE may complicate the design flow, because most designs don't need fast SPICE for clock tree topologies to analyze clock trees.